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1 Step 2 For each of the 144 codeword position X compute Qx S1 Tx The computation of all 144 Qx values can be carried out in parallel in hardware involving XOR circuits Step 3 If Qx D for particular X, then X is a position of error The data at position X are then corrected by an inversion of the data bit (b) Recent Server Machines A typical server machine of IBM eServer z900 and z990, whose dependable system structure is based on the former server IBM S/390 G5 and G6, has the strategy to enable continuous reliable operation, supported by the following building blocks [MUEL99, ALVE02, FAIR04]: Error prevention Error detection Error recovery Problem determination Service / support Change management Measurement mail integrating tobuild usps onecode solution barcode for net .

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Bus interface between L2 cache and memory controller: simple parity-check code for command and status bus Cryptographic key storage: triplicated key data, each appended by simple paritycheck bit Background Memory-Scrubbing and Sparing In main memories the dynamic form of paring is performed via background scrubbing, a process of error avoidance The memory-scrubbing process serves two functions The rst function is to eliminate the accumulation of soft errors in the memory chip The purpose is to reduce the likelihood of the alignments of existing soft errors and future hard or soft errors The second function of scrubbing is to identify and record hard errors in the memory chip Multiple hard errors are prime targets to line up in the same ECC word because they can result in uncorrectable error events Error counts are accumulated while scrubbing, and DRAMs with high counts are spared.

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